1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory device having an error checking and correction circuit.
2. Description of the Related Art
Recently, in accordance with an increase in storage capacity of dynamic random access memory (DRAM) devices, an error checking and correction (ECC) circuit has been provided for the DRAM device to realize high reliability. This ECC circuit is used to detect (check) and correct an error bit of data stored in the DRAM device by an error correction code generated by using syndrome, and the like.
In the above DRAM devices, an ECC circuit, a syndrome generation circuit, and a syndrome decoder circuit are, for example, positioned at the center of a chip, data output from the data bus amplifiers are transferred to the syndrome generation circuit through the common data bus lines, and data correction signals output from the ECC circuit are transferred to the write amplifiers through the common data bus lines. Note, the number of the common data bus lines is so large, e.g., 64, that an occupancy area of the common data bus lines becomes large. Further, the common data bus line is provided so long (for example, one side of the chip, e.g., 10 mm), that the capacitance of each common data bus line becomes large and driving currents thereof becomes large. Consequently, in the above DRAM device, a large scale integration cannot be realized and power consumption becomes large.